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Detailed Description
X-Ref Target - Figure 1-7
UG771_c1_07_022211
Figure 1-7:
Fan Power Connector (J101)
FPGA Configuration
[ Figure 1-2 , callout 2 ]
The FPGA is configured in JTAG mode only using one of the following options:
?
?
?
?
Platform Cable USB
Parallel Cable IV
Parallel Cable III
System ACE controller
Detailed information on the System ACE controller is available in
DS080 , System ACE CompactFlash Solution .
The FPGA is configured through one of the aforementioned cables by connecting the cable
to the JTAG cable connector, J1.
The FPGA is configured through the System ACE controller by setting the 3-bit
configuration address DIP switches (SW3) to select one of eight bitstreams stored on a
CompactFlash memory card (see Configuration Address DIP Switches, page 19 ).
The JTAG chain of the board is illustrated in Figure 1-8 (the four System ACE interface
isolation jumpers described in JTAG Isolation Jumpers are not shown). Shorting pins 1–2
on header J162 automatically bypasses the FMC modules, GTH transceiver power supply
module and GTX transceiver power supply module in the chain.
ML628 Board User Guide
UG771 (v1.1) February 19, 2014
www.xilinx.com
17
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